System Verilog- NOC design (8 bit split bus)

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Hello! Please check my reviews to know a bit about me! Thank you

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction. CSI-2 transmitter and receiver(6months) The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards eMMC Host Controller and Device controller(3months) The project is to develop eMMC host and Device controller IP according to the JEDEC standards. Mobile camera–testing(3months) The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies High resolution camera(6.5months) The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor -Test project for DDR2 accesses -Development of calibration module -Development of chain control module -Development of control signal generator -Development of Generic LUT module -Development of Divider radix-2 algorithm -Development of atan calculator -Development of MCB reader state machine Color Pipeline(15months) The project is to develop 2D and 3D image processing algorithms on Aptina sensor -Development of Generic Frame Buffer pCore -Development of data compression and data packing pCore -Development of data packing pCore Video Processing Unit(13 months) -Improvement in algorithms to reduce FPGA resource utilization and decrease latency

I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 10 years experience in digital design and well acquainted with ISE 14.5, NCverilog, Vivado 2013.4, Altera Quartus 13.0sp1, EDK embedded tools & worked on Virtex-6 ML605, Virtex-5 LX110T, Virtex-4 ML401 , Spartan6, Spartan 3E, SOC Znyq Zedboard and MicroZed boards. I have completed 1G data traffic project where in-depth IEEE Ethernet 802.3 packet parsing is done according to rule set defined for voice & data packets. Each TCP, UDP and SIP packet is processing and transmits to destination and vice versa at receiving end. Xilinx Ethernet core is used only for capturing of packet from FPGA. The clock frequency here is 125Mhz for each sample. Please share the project detail. I can work online if it is suitable for you. I am free can start work immediately and can work upto 60 hrs per week. Further we can discuss it and I look forward to receiving your response. Regard Mahar

What exactly do you require ? A verification environment ? Will you provide the design ? Or do you also want the design ?

Over 2.5 years of experience in Verilog RTL Design, Microcontroller Projects and Algorithm Design in MATLAB in Industry and Academia. My past projects include: - PHY Layer Design on FPGA for Software Defined Radio Project for Center for Advanced Research in Engineering, Islamabad - Content Aware Image Processor Design on FPGA and ASIC for my Masters Thesis - Memory controller design for Hybrid NAND Flash Disks - Interfacing Gyro+Accelerometer using Arduino Uno for Human Focus International - Algorithm Design in Simulink and MATLAB

I have module IP for CRC calculation. i think it easy with me...please contact me to get draft version about CRC. Thanks Vu

Hello, I can do this project. I am expert in FPGA, VHDL, Verilog. I have done no of project on this technology. Please open your chat box for more discussion. I have 4 year experience in this field. I can do your project easily.