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Solving FPGA output module

$30-250 USD

Zaprt
Objavljeno pred več kot 5 leti

$30-250 USD

Plačilo ob dostavi
1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12
ID projekta: 18272630

Več o projektu

3 ponudb
Projekt na daljavo
Aktivno pred 5 leti

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3 freelancerjev je oddalo ponudbo s povprečno vrednostjo $162 USD za to delo
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Am a solid independent specialist, I am so eager to function as a consultant, I am a diligent employee, inspired by meeting set focuses inside due dates, as it gives me a feeling of achievement. I focus on points of interest and guarantee that my work will fulfil your desires. I likewise begin taking lessons to turned into an Experienced FPGA/Verilog/VHDL Engineer hand, to build up my aptitudes around there. I can state I am a genuine all-around collaborator with the capacity to deal with all parts of business while expanding general profitability with effective work.
$30 USD v 2 dneh
4,9 (12 ocen)
4,6
4,6
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Hello there, I am krishna from Logictronix.com. We already have designed Sigma Delata ADC with 16 channel ADC channel on VIVADO and Zynq Architecture. We can do your project, We also have ZeddBoard FPGA which can initially target your project requirement. Your design also need same Zynq device as xcz7020CLG484-1. Let us know your interest. For completing this project minimum 4 days is needed.
$180 USD v 4 dneh
4,8 (1 ocena)
1,4
1,4
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HI Sir , I am interested in your project , i am skilled in Xilinx and verilog . I have been developing project for Spartan 6 FPGA , both HW and firmware. Regards ,
$277 USD v 3 dneh
0,0 (1 ocena)
0,0
0,0

O stranki

Zastava CHINA
Shenzhen, China
0,0
0
Član(ica) od dec. 1, 2018

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