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Building a HEVC Intra prediction block for FPGA

$30-250 USD

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pred približno 8 leti

$30-250 USD

Plačilo ob dostavi

Designing a HEVC Intra prediction block in Verilog for a Xilinx Nexys Video FPGA board. FPGA should take a picture as input and should give encoded picture as output.

ID projekta: 10126474

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3 ponudb

Projekt na daljavo

Aktivno pred 8 leti

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3 freelancerjev je oddalo ponudbo s povprečno vrednostjo $250 USD za to delo

Zastava AUSTRALIA

I am an experienced VLSI engineer with strong verilog and FPGA architecture knowledge. I hope I can deliver a good result for your project.

$150 USD v 4 dneh

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Zastava UNITED STATES

Fresno, United States

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Plačilna metoda je verificirana

Član(ica) od feb. 26, 2016

Verifikacija stranke

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