project is to design the logic for an FPGA that will implement the test pattern shown below. The colors and sizes do not need to exactly match.

I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC. I use Quartus II and Vivado IDEs accordingly. I test timing compliance through timing analysis . I deliver tested , neat and well-commented code that can be reused or modified for future development. More to be discussed once you contact me . BR, M.T.

I have high proficiency in Electrical Engineering,Mechanical Engineering, Verilog/VHDL Once you share the project, I will have a look & confirm if I can do it. I’m honest, creative and a unique person to carry out your tasks given to me. Leaving your project on our hand is a privileged; we'll make sure that the project is done in a perfect way and do our best until you satisfied. I would love to discuss this project with you and meet your exact requirements. I am confident I can provide you with top notch materials that will fit your needs. I pride my work on being professional, of the highest quality and always delivered on time. you can hire me dirctly through this link https://www.freelancer.com/u/olaideejiwole

Yes sir got it will do project is to design the logic for an FPGA that will implement the test pattern shown below. The colors and sizes do not need to exactly match.