Punam S.

Total experience of 7 years into Semiconductor and EDA Industry. Throughout experience in module level RTL coding , verification of ASIC designs and VIP Development. 4+ years of experience in constrained random based Functional verification in front end ASIC flow. Well conversed with verification methodologies such as OVM, UVM for more effective and re-usable test bench component knowledge and familiarity of Functional coverage concepts and System Verilog with APB, I2C, OCP, IOSF, JTAG and USB protocols. Assets as a freelancer: 1. Highly motivated to work on my own. 2. Effective and detailed Communication skill. 3. Ability to learn new technology rapidly, work flexibly and take new initiatives. Technical Exposure: 1. Good expertise in C++ programming language. 2. Very Good expertise in verilog and system verilog languages. 3. Good knowledge of Perl scripting. 4. Good expertise in OVM and UVM methodologies.