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hsinchu,
taiwan
Trenutno je 10:57 pop. tukaj
Datum pridružitve februar 28, 2023
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Narasimha N.
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hsinchu,
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Researcher
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Izkušnje
TCAD Engineer
feb. 2019 - jan. 2024 (4 leta, 11 mesecev)
Proficient in TCAD tools for device and circuit simulations
Izobrazba
PhD
(5 let)
Kvalifikacije
Full Custom IC Design
Taiwan Semiconductor Research Institute
2023
IC Design by using Cadence-Virtuoso
VLSI Advanced Processing Equipments
Taiwan Semiconductor Research Institute
2023
Advanced processing equipments usage and processing
Python
Google
2023
Certificate Course
Publikacije
Device-simulation-based machine learning technique for the characteristic of line TFETs
IEEE Access
With the rapid growth of the semiconductor manufacturing industry, it has been evident that device simulation has been considered a sluggish process. Therefore, due to downscaling of semiconductor devices, it is significantly expensive to obtain the inevitable device simulation data because it requires complex analysis of various factors.
DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs
Nanotechnology
In this paper, electrical characteristics of a complementary tunneling field effect transistor (CTFET) is studied computationally for the first time. The design of CTFET is carried with 3D vertically stacked channels (multiple) of n-TFET on top of the p-TFET with gate-all-around (GAA) nanosheet SiGe options. The CTFET technology (using CFETs) is examined for emerging technology nodes as a potential alternative to conventional TFETs.
Design and exploration of vertically stacked complementary tunneling field-effect transistors
Applied Physics Express
The purpose of this letter is to study the design and explore vertically stacked complementary tunneling field-effect transistors (CTFETs) using CFET technology for emerging technology nodes. As a prior work, the CTFET's device-level simulations are implemented and deliberated in strict compliance with the experimental settings.
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