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$70 USD/uro
Zastava ARGENTINA
san rafael, argentina
$70 USD/uro
Trenutno je 12:49 pop. tukaj
Datum pridružitve julij 3, 2018
0 Priporočila

Fernando Andres G.

@FernandoAGV

annual-level-two.svg
verified.svg
 5,0 (7 ocen)
8,5
8,5
100%
100%
$70 USD/uro
Zastava ARGENTINA
san rafael, argentina
$70 USD/uro
100 %
Opravljeno delo
100 %
V okviru proračuna
100 %
Pravočasno
20 %
Stopnja ponovnega najema

Sr. Digital Hardware Design / Firmware Engineer

Hi there! My name is Fernando, I'm a Senior Electronic Engineer with advanced knowledge of digital design and experience in embedded systems implemented with DSP, FPGA and Microcontrollers. I have 10+ years of experience working in the Aerospace, IoT (Internet of Things) and IC (Integrated Circuits) industries, participating in multidisciplinary teams and performing the following tasks: - Team Leadership - Project Management - Digital Signal Processing (FIR and IIR Filtering, LMS, FFT) - Electronic / Circuit Design - High-speed Digital Design on FPGAs (VHDL/Verilog) - Embedded Software Development (C programming) - PCB Layout - MAIT (Manufacturing, Assembly, Integration and Test) - Validation in Laboratory - Writing of Technical Documentation I love working on complex and challenging designs. I have the ability to solve problems, seriousness and responsibility to carry out the work in the best way. You can trust that I will give my best to deliver a work that exceeds your expectations. My working hours are Monday to Friday from 9:00 am to 6:00 pm (GMT -3). FEATURED REVIEW "Fernando has been a real pleasure to work with on this project. He's very meticulous in his work which is a critical attribute to being a successful engineer/consultant. He's capable of high quality deliverables along with excellent documentation/communication skills. I will continue to leverage his expertise in the future provided he enjoys the work he is doing for Power Down Semiconductor as the relationship has to work both ways." - David H.
Freelancer Verilog / VHDL Designers Argentina
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Portfelj

10646193
Ethash Assist (AXI-Stream Version)
Ethash Assist (AXI-Stream Version)
9396839
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
6029176
The implementation of a feedback ANC applied to a headset was done using a low cost, 16 bits, fixed point DSP StarCore MSC7116 from Freescale. The DSP program runs over SmartDSP (RTOS). The board has also integrated the stereo 16 bit CODEC AK4554. The noise inside the headset may vary over time because the external noise has changed, or because the headset has moved, changing its acoustic transfer function. The ANC system must be able to adapt to these changes, modifying the produced anti-noise signal accordingly. The ANC adaptive filters are made of a Finite Impulse Response (FIR) filter with varying coefficients. In order to compensate the effect of S(z) the input to the adaptive algorithm has to be affected (filtered) in the same way as the controller´s output. The modified algorithm is then called Filtered x Least Mean Squares (FxLMS) algorithm. As S(z) is unknown and may vary on time, it is identified by a second adaptive system and a copy of its transfer function, S^(z), is intr
Adaptive Narrowband ANC System
The implementation of a feedback ANC applied to a headset was done using a low cost, 16 bits, fixed point DSP StarCore MSC7116 from Freescale. The DSP program runs over SmartDSP (RTOS). The board has also integrated the stereo 16 bit CODEC AK4554. The noise inside the headset may vary over time because the external noise has changed, or because the headset has moved, changing its acoustic transfer function. The ANC system must be able to adapt to these changes, modifying the produced anti-noise signal accordingly. The ANC adaptive filters are made of a Finite Impulse Response (FIR) filter with varying coefficients. In order to compensate the effect of S(z) the input to the adaptive algorithm has to be affected (filtered) in the same way as the controller´s output. The modified algorithm is then called Filtered x Least Mean Squares (FxLMS) algorithm. As S(z) is unknown and may vary on time, it is identified by a second adaptive system and a copy of its transfer function, S^(z), is intr
Adaptive Narrowband ANC System
The implementation of a feedback ANC applied to a headset was done using a low cost, 16 bits, fixed point DSP StarCore MSC7116 from Freescale. The DSP program runs over SmartDSP (RTOS). The board has also integrated the stereo 16 bit CODEC AK4554. The noise inside the headset may vary over time because the external noise has changed, or because the headset has moved, changing its acoustic transfer function. The ANC system must be able to adapt to these changes, modifying the produced anti-noise signal accordingly. The ANC adaptive filters are made of a Finite Impulse Response (FIR) filter with varying coefficients. In order to compensate the effect of S(z) the input to the adaptive algorithm has to be affected (filtered) in the same way as the controller´s output. The modified algorithm is then called Filtered x Least Mean Squares (FxLMS) algorithm. As S(z) is unknown and may vary on time, it is identified by a second adaptive system and a copy of its transfer function, S^(z), is intr
Adaptive Narrowband ANC System
10646193
Ethash Assist (AXI-Stream Version)
Ethash Assist (AXI-Stream Version)
9396839
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
Design and development of a controller based on FPGA (Spartan 6) for testing displays that have a MIPI DSI interface. The client needed to test displays of different models of smartphones from a well-known brand.
Tester for MIPI DSI Displays
6029176
The implementation of a feedback ANC applied to a headset was done using a low cost, 16 bits, fixed point DSP StarCore MSC7116 from Freescale. The DSP program runs over SmartDSP (RTOS). The board has also integrated the stereo 16 bit CODEC AK4554. The noise inside the headset may vary over time because the external noise has changed, or because the headset has moved, changing its acoustic transfer function. The ANC system must be able to adapt to these changes, modifying the produced anti-noise signal accordingly. The ANC adaptive filters are made of a Finite Impulse Response (FIR) filter with varying coefficients. In order to compensate the effect of S(z) the input to the adaptive algorithm has to be affected (filtered) in the same way as the controller´s output. The modified algorithm is then called Filtered x Least Mean Squares (FxLMS) algorithm. As S(z) is unknown and may vary on time, it is identified by a second adaptive system and a copy of its transfer function, S^(z), is intr
Adaptive Narrowband ANC System
The implementation of a feedback ANC applied to a headset was done using a low cost, 16 bits, fixed point DSP StarCore MSC7116 from Freescale. The DSP program runs over SmartDSP (RTOS). The board has also integrated the stereo 16 bit CODEC AK4554. The noise inside the headset may vary over time because the external noise has changed, or because the headset has moved, changing its acoustic transfer function. The ANC system must be able to adapt to these changes, modifying the produced anti-noise signal accordingly. The ANC adaptive filters are made of a Finite Impulse Response (FIR) filter with varying coefficients. In order to compensate the effect of S(z) the input to the adaptive algorithm has to be affected (filtered) in the same way as the controller´s output. The modified algorithm is then called Filtered x Least Mean Squares (FxLMS) algorithm. As S(z) is unknown and may vary on time, it is identified by a second adaptive system and a copy of its transfer function, S^(z), is intr
Adaptive Narrowband ANC System
The implementation of a feedback ANC applied to a headset was done using a low cost, 16 bits, fixed point DSP StarCore MSC7116 from Freescale. The DSP program runs over SmartDSP (RTOS). The board has also integrated the stereo 16 bit CODEC AK4554. The noise inside the headset may vary over time because the external noise has changed, or because the headset has moved, changing its acoustic transfer function. The ANC system must be able to adapt to these changes, modifying the produced anti-noise signal accordingly. The ANC adaptive filters are made of a Finite Impulse Response (FIR) filter with varying coefficients. In order to compensate the effect of S(z) the input to the adaptive algorithm has to be affected (filtered) in the same way as the controller´s output. The modified algorithm is then called Filtered x Least Mean Squares (FxLMS) algorithm. As S(z) is unknown and may vary on time, it is identified by a second adaptive system and a copy of its transfer function, S^(z), is intr
Adaptive Narrowband ANC System

Ocene

Spremembe shranjene
Prikazanih je1 - 5 od 7 ocen
 Filtriraj ocene po:
5,0
$161.468,79 USD
FPGA prototyping and write memory BIST and boot loader code for openMSP ASIC project.
Fernando has been a real pleasure to work with on this project. He's very meticulous in his work which is a critical attribute to being a successful engineer/consultant. He's capable of high quality deliverables along with excellent documentation/communication skills. I will continue to leverage his expertise in the future provided he enjoys the work he is doing for Power Down Semiconductor as the relationship has to work both ways.
Electronics
Verilog / VHDL
Microcontroller
Electrical Engineering
FPGA Coding
Avatar uporabnika
Zastava David H.
@huffdave
•
pred 3 leti
5,0
€1.150,00 EUR
Basic program for Lattice ispLSI1032e
I am very pleased with Fernando, he completed the job, his expertise was spot on and he provided extra support to help me debug some of my issues. I will hire him again for sure
Electronics
Verilog / VHDL
Microcontroller
FPGA
FPGA Coding
L
Zastava Loic C.
@Loic74650
•
pred 4 leti
5,0
£350,00 GBP
Project 23141693 has been deleted
This guy is the best at what he does, when he says he will deliver to a standard beyond your expectations this is without a doubt an understatment - price is therefore justified completley and he is a very flexible and easy communicator, very proffessional and friendly - if he has a skill set you are looking for he is your guy!
Avatar uporabnika
Zastava Mansour A.
@omarnoor2000
•
pred 4 leti
5,0
$150,00 USD
Write somewhat complex VHDL code to be tested on Altera DE2 board
Fernando is very thoughtful with his approach and asks many questions to ensure you are getting what you need. He produced a quality VHDL code for me and I am very satisfied. I will definitely look for Fernando if I need more coding work completed.
Electronics
Verilog / VHDL
Microcontroller
Electrical Engineering
FPGA
Avatar uporabnika
Zastava Michael S.
@Mkthomassmith
•
pred 4 leti
5,0
$341,00 SGD
Project for Fernando Andres G.
Super efficient and trustworthy . You won't have to worry with his deep knowledge and understanding of coding. He delivers everything that i needed with guidance too. I initially hired a freelancer with 60+ reviews but he didn't complete my job as agreed and mia-ed. Eventho Fernando has only 3 reviews but his standard and level of work is really professional. I recommend him to all of you out there that needs help on hardware programming. Thanks again.
C Programming
Engineering
Verilog / VHDL
Manufacturing Design
+1 več
Avatar uporabnika
Zastava Adol Y.
@joviyeung
•
pred 4 leti

Izkušnje

Sr. Digital Design Engineer / Consultant (Freelancer.com)

POWER DOWN SEMICONDUCTOR
maj 2021 - Trenutno
- Test and characterization of PDS430E2272 ultra-low power MCU. - PDSemi is designing the world's lowest power FPGA devices. Its LPP1K design is functionally equivalent to the Lattice Semi iCE40LP1K, but with >90% lower power consumption. A detailed analysis of its architecture is underway. - Ongoing development in Python of a SRAM compiler for TSMC 65nm technology.

Sr. Electronic Engineer

SKYLOOM GLOBAL CORP.
avg. 2022 - sep. 2022 (1 mesec, 1 dan)
Electronic engineering services. HV Flyback Power Supply Design.

PDS430E2272 - Sr. Digital Design Engineer / Consultant (Freelancer.com)

POWER DOWN SEMICONDUCTOR
mar. 2020 - avg. 2021 (1 leto, 5 mesecev)
PDSemi is developing ultra-low power ICs. Through freelancer.com I worked in the first part of the company, the PDS430E2272 16-bit MCU, doing the following main tasks: - Digital architecture design; - RTL development in Verilog of digital blocks; - FPGA prototyping; - Memory BIST and bootloader code development; - Scripts development in Python.

Izobrazba

Electronic Engineer

Universidad Nacional de Córdoba, Argentina 2001 - 2011
(10 let)

Electronic Technician

Argentina 1994 - 1999
(5 let)

Publikacije

FxLMS and MFxLMS Stability Constrains when used in Active Noise Control

IEEE
This paper presents a comparison of the stability of the MFxLMS and FxLMS algorithms, applied to the low frequency narrowband Active Noise Control (ANC). This work focuses on the study of the secondary path in a headset, and the effect of its variations in the system's stability. The analysis is completed with simulations that support the conclusions. https://ieeexplore.ieee.org/document/6502805

Adaptive Narrowband ANC, Design and Implementation Issues

IEEE
This paper presents the design and implementation of an adaptive feedback Active Noise Control (ANC) to cancel the low frequency narrowband noise remaining inside a headset shell. The implementation issues were addressed and tested on a commercial fixed point Digital Signal Processor (DSP). https://ieeexplore.ieee.org/abstract/document/5993725

Stopite v stik s/z Fernando Andres G. glede vašega dela

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Top spretnosti

Verilog / VHDL 10
FPGA 9
C Programming 5
Electronics 5
Engineering 4

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