RISC Pipelined Processor Verilog

Hey there, I'm a professional computer engineer who has implemented several CPU architectures in Verilog and VHDL. I'd be glad to take a look your code and why it wouldn't be compiling. Please contact me with more details like what software and implementation you were using, just in case we have differing results and can whittle it down. Thanks, Chris

I have experience in CPU Design, I can fix it within 1 week. RTL will be verified and compiled by Modelsim tool.