Implementation of Gradient descent optimizer on FPGA in verilog code which is synthesizable
₹1500-12500 INR
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Objavljeno pred več kot 1 letom
₹1500-12500 INR
Plačilo ob dostavi
I need to design gradient descent optimizer on FPGA in verilog language and code should be synthesizable. entire design should be pipelined. Input and outputs should be in single precision floating point representation. loss or cost function is mean square error loss for 2D variables, minimise the above cost functions to achieve the optimised value.
I have developed gradient descent optImizer on python , below attached file is code of it. I want same implementation in verilog
I can do it. As 9+ years experiences in these field. I can give good quality work. I have read the guidelines of your work.I believe that i can provide you the best quality works you are anticipating from this platfrom give me a chance to show you the best i can do at your service.
Hi,
Im a FPGA designer having 5years of experience. Please check my profile for to know more about my projects.
Please contact me for further discussion.
From Kerala.
Regards,
Athul. b