Help to create circuit using Bit scope

$12-30 SGD

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pred več kot 5 leti

$12-30 SGD

Plačilo ob dostavi

Verify if my circuit is correct and guide to resolve the errors. Measure the gain of an inverting amplifier at an input frequency through Experiment and print out time-domain input and output waveform

Circuit Design

Electrical Engineering

Electronics

Microcontroller

Verilog / VHDL

ID projekta: 18003464

Več o projektu

3 ponudb

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Aktivno pred 5 leti

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@loi09dt1

A highly-skilled FPGA engineer with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, PLP Tools, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, CMOS VLSI Design, Cadence Virtuoso, Layout XL, Digital IC Design from RTL to GDSII, Analog IC Design. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + Single/Multicycle/Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other FPGA projects

$51 SGD v 1 dnevu