technical content writer for the verilog, system verilog,uvm and ovm with project examples

Zaprto Objavljeno pred 5 letoma/leti Plačilo ob prevzemu
Zaprto Plačilo ob prevzemu

my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

Article Writing Elektro inženiring Pisanje tehničnih vsebin Verilog / VHDL Very-large-scale integration (VLSI)

ID projekta: #17620898

Več o projektu

10 predlogov Oddaljen projekt Aktiven pred 5 letoma/leti

10 freelancerjev ponuja v povprečju za ₹7811 na tem delu

loi09dt1

Hi, I am a highly-skilled FPGA engineer with 6+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. An FPGA/Verilog/VHDL Codem Več

₹7777 INR v 1 dnevu
(149 ocen)
6.7
raulbehl

Hello! I am a graduate in Electronics and Instrumentation Engineering from BITS Pilani Goa Campus, and am currently working as a freelance CPU Design Engineer. I am enthusiastic about Computer Architecture, Process Več

₹7777 INR v 7 dneh
(85 ocen)
6.3
demossoft

I have reviewed your bid request and I am very interested in your project. I was trained overseas and have an extensive customer service record so contact me so we can discuss further or begin. Relevant Skills and Exp Več

₹11111 INR v 9 dneh
(38 ocen)
5.2
SqUa11

Hi, I have 5 years experience in the digital design field please contact me for more details, Regards, Mohamed

₹12500 INR v 3 dneh
(66 ocen)
5.2
EslamElGeddawy

Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Throughout my 3+ years of experie Več

₹8000 INR v 3 dneh
(7 ocen)
4.5
engineeringexp

Master in Engineering, Electrical and Electronic Engineer, who is dynamic, reliable, resourceful, committed and organized with enthusiastic approach to succeed with a pleasant attitude. Possessing excellent analytical Več

₹7777 INR v 3 dneh
(12 ocen)
4.4
janetyeah

I am working in the ASIC industry. I have been working in Cadence for two years. The project is definitely in areas of my expertise. I am very familiar with Verilog, Systemverilog, ovm and uvm. This is my first bid Več

₹7777 INR v 7 dneh
(0 ocen)
0.0
ShankarVHDL

I done many projects documents with DO 254 standard

₹5555 INR v 7 dneh
(0 ocen)
0.0