Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Najem Verilog / VHDL Designers

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    Creating Circuit in Logisim 6 dni left
    VERIFICIRAN/A

    Build a calculator that can add and subtract decimals of up to 5 decimal digits. The calculator should have a display of 6 decimal digits. There should a number pad with digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and three possible operations, + (addition), - (subtraction), = (equals). The flow of the operations should be as follow: While typing the number it should be displayed right aligned, extendin...

    €52 (Avg Bid)
    €52 Povprečna ponudba
    5 ponudb

    i want to hire experienced person of circuit designing and in embedded system contact me for more information chate

    €323 (Avg Bid)
    €323 Povprečna ponudba
    19 ponudb
    Vhdl project 5 dni left

    It is a cluster related vhdl project.

    €241 (Avg Bid)
    €241 Povprečna ponudba
    12 ponudb

    i already have the 90% of the code just need to finish 10% and guide me on running the code my my board

    €57 (Avg Bid)
    €57 Povprečna ponudba
    5 ponudb

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    €126 (Avg Bid)
    €126 Povprečna ponudba
    5 ponudb

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comp...

    €123 (Avg Bid)
    €123 Povprečna ponudba
    2 ponudb
    €34 Povprečna ponudba
    6 ponudb

    MRAS SYSTEM SIMULATION USING SIMULINK NEEDED You will have 7 days to complete the work defined in scope. Your bid will not be negotiated so please read well before you bid. Payment will be 50/50 after simulation and after writting. Maximum Budget is 250USD

    €336 (Avg Bid)
    €336 Povprečna ponudba
    7 ponudb

    VHDL implemented in altera de2 board

    €309 (Avg Bid)
    €309 Povprečna ponudba
    5 ponudb

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    €69 (Avg Bid)
    €69 Povprečna ponudba
    3 ponudb

    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

    €21 (Avg Bid)
    €21 Povprečna ponudba
    6 ponudb

    The project has a few basic functions. 1. maintain a specific temperature 2. fire a signal to a solenoid valve in particular (adjustable) intervals. other basic functions like on off etc

    €168 (Avg Bid)
    €168 Povprečna ponudba
    43 ponudb

    Verilog simulation of two action-reaction processes

    €26 (Avg Bid)
    €26 Povprečna ponudba
    6 ponudb

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €157 (Avg Bid)
    €157 Povprečna ponudba
    7 ponudb

    Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of adc data. The input waveform is shown in the figure. The dif...

    €227 (Avg Bid)
    €227 Povprečna ponudba
    8 ponudb

    Vhdl is needed

    €24 (Avg Bid)
    €24 Povprečna ponudba
    6 ponudb