microcontroller programs employing peripherals ADC and PWM peripherals Scheduling and concurrency using FSM RTOS Wireless systems and IoT State machines( Verilog) Digital Design using Verilog and software Programming FPGAs Embedded processors
Would like someone who can code in verilog-A for TFET within limited time
I am looking to hire someone to go through the vitter algorithm of the dynamic huffman coding and implement the encoder(compulsory) and decoder(optional) . I am willing to explain you the details of the algorithm in depth once we connect . there are several articles that I have referred to but the wikipedia description is pretty accurate so I provide the link here. There is a visual representation of the same algorithm in the other links and some accompanying text explaining. You are required to go through the vitter algorithm and implement the same. Links : 1) 2)
More details will be shared later.
I have written the code for a simle SPI Master in verilog and also included a testbench. I want you to: 1) Add a Clock Divider to it, so that the output SPI frequecy is 1MHz 2) There are 3 SPI commands: (1) one write command, (2) multiple write command, (3) one read command. Modify the SPI master Verilog code to implement these 3 commands. Ideally, I want to specify (i) write or read, (ii) number of bytes if write command, (iii) address, (iv) data, then the code will automatically generate the correct checksum and dummy bytes. Would appreciate if the work could be finished as soon as possible. Thanks!
Design, simulate and verify a synchronous digital system that detects and recognizes your student ID as password that can be used to generate an output signal. The student ID is entered to the system sequentially and synchronized to the master clock for proper operation of the system. The system is expected to generate an output logic High for 3 clock cycles if the ID sequence is detected correctly. The system will then return to the wait state, where it waits for a new sequence to be entered by user. Use any of the student ID from the group members in this design. You are free to add any additional features to your system as deemed appropriate.
hi i want to create one image processing code for attached images . final image has different. This small dot can be any where in this white line . can you do this? code should have to find this dot in blue red ,yellow etc apart from can use only Verilog or VHDL here please send your price for this and time . Then we can start.
, I need help with, Single cycle data-path design of CPU with assembly code in Verilog.
Need an expert in VHDL with Microprogrammed control unit and hardwired control unit design for a 1 bit processor
Need to implement neural network testing on verilog. Need verilog coding. Training and testing done in matlab. And then testing part again done in verilog. And then compare the computational time of matlab and verilog
Design an 8 bit microprocessor in VHDL with two execution stages: fetch and execute. There are two shared buses, one for address and one for data. Both the buses are connected to an external memory. There is a pdf attached which provides a more information and the expected structure of the microprocessor. Any other questions please ask in chat.
These are just 3 simple questions needed to be completed on the topic of sequential circuits in Verilog. I have to submit this in 2 hours, so if you can do it quickly please accept this offer it is very simple.
Control DC motor by pulse frequency modulation (PFM) IN VHDL . I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite) End of the project I need a report
Top cell : alu I/O: bit 15 is the most significant bit. INPUTS: A(15:0) , B(15:0) , alu_code(4:0) ; OUTPUTS: C(15:0) overflow TOP MODULE: 16-bit Adder Module PRIMARY SIGNALS: BUS inputs/outputs and additional signals BUS signals: bit 15 is the most significant bit. All bus signals are named with upper case letters INPUTS: A[15:0], B[15:0],CODE[2:0] OUTPUTS: C[15:0] More details in Chat!
We are a research gr...working human study involving debugging assistance for Verilog designs. The study involves asking designers to debug mistakes in circuit descriptions, either with or without some form of debugging assistance. The debugging hints can take the form of highlighting the wire or register name with the bug, or highlighting several lines of code likely containing the bug. We are hoping to figure out what forms of debugging assistance work best in helping hardware designers fix mistakes efficiently, and eventually hope to integrate our findings into a learning tool aimed at teaching novices how to write Verilog descriptions. The study is expected to take around 45 minutes to an hour to complete, and we will compensate people familiar with Verilog $25 for...
This is a final year project. We are struck with simulation. Need to debug our program, or else develop the project from scratch. I am attaching the code that we have wrote for your reference. We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2. There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'. From what I understood, the main issue is the interconnection between all the modules.
This project requires the student to implement a 10-bit counter design using VHDL. The counter will have the ability to count up and down from 0 and 1000. This requires the utilization of 16 slide switches and the center push button of the Basys3 board. The 10 right-most switches (SW0 – SW9) will be used to input a preset value to the counter or the ALU. SW0 represents the LSB and SW9 represents the MSB of the input value. The center push button (BTNC) is used as the manual clock for the counter. The count should increase or decrease (depending on the selector switch, SW13) by 1 on every rising edge of this button.
Using ISE design suite. Design an 8-Bit ALU (x and y are inputs and Result is output), based on modular arithmetic and logic circuits and 8x1 line multiplexer, in VHDL. Add comments to your code whenever required. Design a test bench to verify your designed circuit functionality. Add simulation results screen shot. ** I will share more details if you will do it
I need help with my project. You must be good at RISC-V and Verilog. The project is related to Cache. Please check the file
i need help in Implement MIPS processor pipeline and instruction and data caches, using VHDL. i will provide more details in the chat.
This is a simple project in Verilog using System Verilog features as well. We are given the base sv file with a testbench as well, we just have to complete the file with the required code to complete the project.
I am looking for a real-time A-law/U-law encoder written in VHDL for implementing in a Lattice XP2 FPGA. The input to the encoder will be 16 bit PCM16, the output will be 8 bit a-law/U-law. The PCM16input will comprise of 24 channels. The CODEC will have 1 16 bit input. The 2k channels will be fed into the codec sequentially in blocks of 32 16bit samples. The CODEC shall handle a total of 10 Megasamples/second in real time. Each block of 32 16bit PCM data will be accompanied with a 4 bit channel number 0-23. The 8 bit companded output should have an extra 4 bit output that will hold the channel address that corresponds to the PCM channels from which it was created. The target FGA is a Lattice XP2-8 but the code will be demonstrated in the Lattice XP5 eval board as attached.